
module RegisterFile(
input Clk, 
input Reset,
input [31:0] PortIn,
input RegWrite, // se�al de control
input RegRead,
input [4:0] ReadRegA, // primer registro fuente Operando A rs
input [4:0] ReadRegB, //primer registro fuente Operando B rt
input [4:0] WriteRegister, // registro destino resultado rd
input [31:0] WriteData, //dato
output [31:0]ReadDataA, // a la alu 
output [31:0]ReadDataB, // a la alu
output wire[31:0] PortOut
);

parameter [5:0] REG_ANCHO = 32;
parameter [5:0] REG_LARGO = 32;

reg [REG_ANCHO-1:0] RegFile [0:REG_LARGO-1];


always @(posedge Clk)
 begin
     
  if (Reset)
      RegFile[0] <= 0;// reg base

				
  if(RegWrite) 
    if ((WriteRegister != 5'h 00) && (WriteRegister != 5'h 1F))
      RegFile[WriteRegister] <= WriteData;
    else if ((WriteRegister == 5'h 00))
        RegFile[WriteRegister] <= 0;
     //else//if /*(!RegRead)*/
        RegFile[31] <= PortIn;
 end

assign ReadDataA = RegFile[ReadRegA] ;
assign ReadDataB = RegFile[ReadRegB] ;

assign PortOut =  RegFile[30] ; 

//assign ReadDataA = (WriteRegister != 5'h 1E) ? RegFile[ReadRegA] : RegFile[30] ;
//assign ReadDataB = (WriteRegister != 5'h 1E) ? RegFile[ReadRegB] : RegFile[30] ;
endmodule